The present invention relates to a semiconductor device testing method and apparatus suitable for use in testing semiconductor devices that have built-in fast write and read type memories.
Before entering into an explanation of the prior art to which the present invention pertains, a description will be given, with reference to FIG. 1, of the general outlines of a semiconductor IC tester.
The IC tester, identified generally by TES, comprises a main controller 13, a pattern generator 14, a timing generator 15, a waveform formatter 16, a logic comparator 12, a driver 17, a signal readout circuit 11, a failure analysis memory 18, a logical amplitude reference voltage source 19, a comparison reference voltage source 21 and a device power source 22.
The main controller 13 is usually formed by a computer system and operates under the control of a test program prepared by a user, mainly controlling the pattern generator 14 and the timing generator 15. The pattern generator 14 generates test pattern data, which is converted by the waveform formatter 16 to a test pattern signal of the same waveform as the actual one. The test pattern signal is provided to the driver 17 from which it is output as a waveform of an amplitude value set in the logical amplitude reference voltage source 19 and is applied to a memory under test DUT for storage therein.
A response signal read out of a memory cell of the semiconductor device under test DUT is provided to the signal readout circuit 11, wherein its logical value is read out, that is, sampled by a strobe pulse. The logic comparator 12 compares the thus read-out logical value with an expected value fed from the pattern generator 14. If a mismatch is found between the logic value and the expectation, it is decided that a memory cell of the address from which the response signal was read out is failing, and upon each occurrence of such a failure, the faulty address is stored in the failure analysis memory 18 for use in deciding, after completion of the test, whether the failed cell is repairable.
FIG. 1 is a diagrammatic showing of the tester configuration for one pin alone, but in practice the depicted configuration is provided for each pin of the memory DUT; that is, for each pin the test pattern is input to the memory DUT and the response signal is read out therefrom.
Among semiconductor memories is a memory (hereinafter referred to also as a semiconductor device)of the type that performs the writing and reading of data thereto and therefrom in synchronization with a clock.
FIG. 2 shows how this kind of memory is read out. FIG. 2A depicts pieces of data DA, DB, DC, . . . that are output from (a pin of) memory, respective test cycles TD1, TD2, TD3, . . . being divided off by broken lines. FIG. 2B shows a clock DQS that is output from the memory. As shown, the pieces of data DA, DB, DC, . . . are output from the memory in synchronization with the clock DQS. When the semiconductor IC is in actual use, the clock is used as a sync signal (data strobe) to pass the pieces of data DA, DB, DC, . . . to other circuits.
The testing the semiconductor device of this kind includes an item of measuring time difference or intervals (phase differences) dI1, dI2, dI3, . . . between the rise and fall timing of the clock (hereinafter referred to as a reference clock) DQS and the points of change of the data. The smaller the time differences, the faster the response and consequently the higher the level of performance characteristic. In other words, the grade of the memory under test depends on the above-mentioned time differences.
While the semiconductor device (memory) is in actual use, a clock from a clock source is applied to a circuit in the semiconductor device, from which data is output in synchronization with the clock. Accordingly, in the testing of the semiconductor device by the tester, too, a clock is fed from the tester to the semiconductor device under test and is passed through its internal circuit, thereafter being output therefrom, together with data, as the reference clock DQS for providing the output data to the tester. The tester measures the rise and fall timing of the reference clock DQS and the time intervals dI1, dI2, dI3, . . . between the measured timing of the rise and fall of the reference clock DQS and the points of change of the pieces of data DA, DB, DC, . . .
Since the reference clock DQS is output from the semiconductor device under test after passing through its inside as mentioned above, the rise and fall timing of the reference clock DQS is greatly affected by internal circuit operations of the semiconductor device under test and environmental conditions such as ambient temperature. For example, as depicted in FIG. 3 in which there are shown reference clock pulses DQSA, DQSB and DQSC that are output from individual semiconductor devices under test A, B and C, the reference clock pulses DQSA, DQSB and DQSC are phased apart. This phase difference is caused not only by device-to-device variation but also by the difference in the memory address accessed in the respective semiconductor device and by jitter J of the rise and fall timing of each reference clock that is caused by an increase in the device temperature due to an extended period of operation as indicated by the broken lines.
With the point of measurement set at timing with too wide a margin of safety against such variations or fluctuations in performance characteristics of the devices under test, there is fear of a device of normal operation being decided as defective; the possibility of such a wrong decision gets stronger particularly with an increase in the operating frequency of the device.
Accordingly, it is necessary to accurately measure the time intervals dI1, dI2, dI3, . . . between the rise and fall timing of the reference clock DQS and the points of change of the pieces of data DA, DB, DC, . . . This requires accurate measurement of the rise and fall timing of the reference clock DQS.
To this end, it is customary in the prior art to measure the rise and fall timing of the reference clock DQS while gradually shifting the timing for the application of the strobe pulse to the signal readout circuit of the tester, the measurement results being used to measure the time intervals dI1, dI2, dI3, . . . .
FIG. 4 is a block diagram depicting a conventional arrangement for measuring the rise and fall timing of the reference clock DQS. A level comparator 10 comprises a pair of voltage comparators CP1 and CP2, by which it is decided whether the logical value of the reference clock DQS output from the semiconductor device DUT satisfies normal voltage conditions. The voltage comparator CP1 decides whether the voltage value of the logical xe2x80x9cHxe2x80x9d value of the reference clock DQS is above a normal voltage value VOH. The voltage comparator CP2 decides whether the voltage value of the logical xe2x80x9cLxe2x80x9d value of the reference clock DQS is below a normal voltage value VOL.
These decision results are provided to the signal readout circuit 11, which measures the rise and fall timing of the reference clock DQS. Upon each application thereto of the strobe pulse STB, the signal readout circuit 11 reads out the logical value input at that time.
FIG. 5A shows the reference clock DQS that is provided for each test cycle TD. FIG. 5B shows strobe pulses STB that are applied to the signal readout circuit 11 over a sequence of test cycles TD. The strobe pulses STB are phased xcfx84T apart with respect to the reference clock DQS as depicted in FIG. 5B. That is, for each test cycle the strobe pulse STB is applied to the signal readout circuit 11 to read out (sample) the outputs from the voltage comparators CP1 and CP2. The output-side arrangement of the voltage comparator CP2, though not shown in FIG. 4, is identical with the depicted arrangement of the voltage comparator CP1.
The logic comparator 12 compares the logical value output from the signal readout circuit 11 with a predetermined expected value (in the FIG. 4 example, the logical xe2x80x9cHxe2x80x9d value) and, upon matching, outputs a pass signal PA (FIG. 5C) indicating that the device under test or memory cell is nondefective. Based on the generation timing of the strobe pulse STB1 (FIG. 5B) (the generation timing of the strobe pulse STB being known) to which the signal readout circuit 11 responded to read out the reversal of the output from the level comparator 10 to the logical xe2x80x9cHxe2x80x9d value, the time T1 from the beginning of the test cycle to the generation of the strobe pulse STB1 is detected, and the rise timing of the reference clock DQS is determined accordingly.
The fall timing of the reference clock DQS is detected by starting the retrieval after the reference clock DQS rose to the logical xe2x80x9cHxe2x80x9d value and then by determining, as is the case with the detection of the rise timing, the fall timing based on the generation timing of the strobe pulse STB to which the signal readout circuit 11 responded to read out the reversal of the output from the voltage comparator CP2 to the logical xe2x80x9cHxe2x80x9d value.
As described above, it is conventional to measure the generation timing of the reference clock DQS by the use of the signal readout circuit 11 built in the semiconductor device tester and the timing measuring means that utilizes the strobe pulse STB which is applied to the signal readout circuit 11. Accordingly, the test cycle TD needs to be repeated for measuring only the rise and fall timing of the reference clock DQS, resulting in much time being taken to measure the time intervals dI1, dI2, dI3, . . . .
Furthermore, the rise and fall timing of the reference clock DQS must be measured for all addresses of the memory under test, and in order to exclude the influence of the afore-mentioned jitter by an increase in the device temperature, the measurement of the rise and fall timing of the reference clock DQS needs to be made for all test patterns involved and hence is particularly time-consuming.
It is possible that the time for measuring the rise and fall timing of the reference clock DQS is shortened by widening the phase difference xcfx84T between respective the strobe pulses STB to thereby decrease the number of times the test cycle is repeated, but such widening of the phase difference xcfx84T reduces the accuracy of measurement of the rise and fall timing of the reference clock DQS, resulting in an impairment in the reliability of measured values of the time intervals dI1, dI2, dI3, . . . between the reference clock DQS and the points of change of the pieces of data DA, DB, DC, . . . .
It is therefore an object of the present invention to provide a semiconductor device testing method and apparatus that permit fast, accurate measurement of rising and falling transition points or timing of the reference clock.
Another object of the present invention is to provide a semiconductor device testing method and apparatus that require the one-time-only generation of all test patterns and hence are capable of conducting a pass/fail test on semiconductor devices in a short time and with higher accuracy.
The semiconductor device testing method according to the present invention is to evaluate a device under test in accordance with the phase differences (time differences) between the points of change of respective pieces of data output from the device under test and the points of change (rising or falling transition points) of a reference clock output from the device under test in synchronization with the output data from the device under test. Multiphase pulses are generated which are sequentially phased apart little by little with respect to a predetermined phase position of each test cycle, and the multiphase pulses are used as strobe pulses to sample the reference clock and the phases of the change points of the reference clock are detected from the sampled outputs.
According to an aspect of this invention method, the detected phases of the points of change of the reference clock are converted to the corresponding phase numbers of the multiphase pulses and stored in a memory, from which they are read out to make the evaluation of the device under test based on the above-mentioned phase differences.
The phase detection of the change points of the reference clocks and the conversion of the detected phases to the corresponding phase numbers are carried out for all addresses of the device under test, and the converted phase numbers are stored in the memory at the addresses corresponding to those of the device under test. The above-mentioned phase differences are obtained by reading out the phase numbers from the memory at the addresses corresponding to signals to be applied to the device under test.
Alternatively, the detection of the phases of the points of changes of the reference clocks and the conversion of the detected phases to the phase numbers are performed in the order of generating test patterns that are applied to the device under test at the time of its evaluation. The converted phase numbers are stored in the memory at addresses representing the order of generation of the test patterns, and the above-mentioned phase differences are obtained by reading out the phase numbers from the memory at the addresses indicating the order of generation of the test patterns.
At the timing preset corresponding to the phase numbers read out of the memory, a strobe pulse is generated, and at the timing of this strobe pulse, the logical value of the output data from the device under test is read out to obtain the above-mentioned phase differences for the evaluation of the device under test.
According to another aspect of this invention method, the output data from the device under test is sampled by strobe pulses formed by the multiphase pulses, then the phases of the points of change of the output data, that is, the phases of the rise or fall transition points of the data are detected using the sampled outputs by the multiphase strobe pulses, and the positions of these detected points of change of the output data are converted to the phase numbers of the multiphase pulses, respectively. The phase numbers of the points of change of the device output data and the phase numbers of the points of change of the reference clock are used to make a check to determine if the phase differences between these points of changes of the device output data and the reference clock are within a predetermined range, thereby evaluating the device under test on a pass/fail basis.
The testing apparatus according to the present invention is an apparatus which evaluates a device under test in accordance with the phase differences (time differences) between the points of change of respective pieces of data output from the device under test and the points of change (rising or falling transition points) of a reference clock output from the device under test in synchronization with the output data from the device under test. Strobe pulses formed by multiphase pulses, which are sequentially phased apart little by little, are generated by a multiphase pulse generating means. The reference clock output from the device under test is sampled by the respective strobe pulses in a plurality of reference signal readout circuits, whose outputs are provided to reference phase number output means, from which the phase numbers of strobe pulses immediately following the points of change of the reference clock are output their phases.
According to an aspect of this invention apparatus, the phase numbers output from the reference phase number output means are stored in a memory at addresses corresponding to address signals applied to the device under test. The phase numbers read out of the memory at the addresses corresponding to the address signals applied to the device under test are each used to select predetermined strobe pulse generation timing by a timing selector, and at the selected timing a strobe pulse is generated by a strobe pulse generator. The strobe pulse is applied to a data readout circuit to read out the logical value of the device output data.
Alternatively, the phase numbers output from the reference phase number output means are stored in a memory at addresses representing the order of generation of test patterns applied to the device under test. The phase numbers read out of the memory at such addresses are each used to select predetermined strobe pulse generation timing by the timing selector, and at the selected timing a strobe pulse is generated by the strobe pulse generator. The strobe pulse is applied to the data readout circuit to read out the logical value of the device output data.
According to another aspect of this invention apparatus, plural data signal readout circuit groups, each consisting of plural data signal readout circuits, are provided for each piece of output data from the device under test, and in the plural data signal readout circuits of each group the device output data is sampled by the multiphase strobe pulses corresponding thereto. The outputs from the plural data signal readout circuits for each group are provided to data phase number output means, from which are output the phase numbers of the strobe pulses immediately after the points of change of the output data. The respective phase numbers output from the respective data phase number output means and the phase numbers from the reference phase number output means are provided to a pass/fail results output part, from which is output a decision result as to whether the phase differences between the points of change of the output data and the reference clock fall within a predetermined range.
In the pass/fail results output part the difference between the phase number from the reference number output means and the phase number from each data phase number output means is detected as a phase difference in a phase comparison part, and a check is made in a pass/fail decision part to determine if these phase differences fall within the predetermined range.
In the pass/fail results output part, for example, the phase number from the reference phase number output means is input to one address of plural reference tables and each phase number from each data phase number output means is input to the other address of the corresponding reference tables. From the respective reference tables are output pass/fail results indicating whether the phase differences between the points of change of the reference clock and the respective pieces of output data fall within the predetermined range.